In a reduced instruction set computer (RISC) architecture, microprocessors execute pipelined instructions at a high clock speed. In more modern designs, however, microprocessors rely on parallelism for speed. For example, in a multi-core design, many cores in a single processor package may concurrently execute multiple threads. In another example, in a very long instruction word (VLIW) architecture, a microprocessor may execute multiple components of a microinstruction in parallel.